Can you reverse engineer an ASIC?

Jane Street has released a hardware puzzle challenging participants to reverse engineer an ASIC from its GDS layout file. Solvers must recover a netlist from the physical layout, determine the circuit's purpose, simulate it, and find a specific string output. A warm-up binary adder example with Verilog source, gate-level netlist, and GDS is provided, along with free open-source tools like KLayout and Magic VLSI. Submissions close September 4th, 2026. Jane Street also teases a follow-up competition where participants will design their own chips, with the best entries actually fabricated.

Source: https://blog.janestreet.com/can-you-reverse-engineer-an-asic. 8 Sync News only summarizes and links out; content copyright belongs to the authors and original sources.