Why aren't my two Cortex-A9 cores cache coherent?

A developer documents an attempt to bring up bare-metal Rust on a Terasic DE0-Nano-SOC board's dual Cortex-A9 cores, covering boot via U-Boot, MMU page table setup, cache types, and SMP bring-up. The core problem: after enabling the Snoop Control Unit and starting the second core, the two cores fail to observe a shared AtomicBool consistently, indicating a cache coherency bug the author hasn't yet solved, despite extensive review of Arm documentation and reference driver code. Ends with an open call for readers to spot the mistake.

Source: https://thejpster.org.uk/blog/blog-2026-08-22. 8 Sync News only summarizes and links out; content copyright belongs to the authors and original sources.